versadac  1
versadac - Scalable Recorder Firmware
sla_ssm.h
1 /*******************************************************************************
2 FILE : slatch_ssm.h
3 VERSION : $Id: sla_ssm.h 5305 2006-10-27 12:09:59Z martinto $
4 AUTHOR : Phil Windsor
5 SYSTEM : Diab C for PowerPC under vxWorks
6 DESCRIPTION : Scheduled message classes for driving an AI3 module SPI latch
7 *******************************************************************************/
8 #ifndef __SLATCH_SSM_H
9 #define __SLATCH_SSM_H
10 #include "spismsg.h"
11 
12 /*
13  * The four addresses defined by the chip identify pins ID0 and ID1
14  */
15 enum SlaChipIdEnum
16 {
17  SlaChipSelect0 = 0x00, // ID1 = 0, ID0 = 0
18  SlaChipSelect1 = 0x40, // ID1 = 0, ID0 = 1
19  SlaChipSelect2 = 0x80, // ID1 = 1, ID0 = 0
20  SlaChipSelect3 = 0xC0 // ID1 = 1, ID0 = 1
21 };
22 
23 
24 /*
25  * The following definitions for the SPI latch have been taken
26  * from the 2500 code apart from SLA_PORT_D0 - D7 which are not
27  * bit reversed since we use SPI rather than SCI comms
28  */
29 
30 /*
31  * Bits which define the bits on the port
32  */
33 
34 
35 #define SLA_PORT_D0 (0x01)
36 #define SLA_PORT_D1 (0x02)
37 #define SLA_PORT_D2 (0x04)
38 #define SLA_PORT_D3 (0x08)
39 #define SLA_PORT_D4 (0x10)
40 #define SLA_PORT_D5 (0x20)
41 #define SLA_PORT_D6 (0x40)
42 #define SLA_PORT_D7 (0x80)
43 
44 
45 /*
46  * Definitions within the command part of the message
47  */
48 #define SLA_BIT_CO7 (SLA_PORT_D7)
49 #define SLA_BIT_CO6 (SLA_PORT_D6)
50 #define SLA_BIT_CO5 (SLA_PORT_D5)
51 #define SLA_BIT_CO4 (SLA_PORT_D4)
52 #define SLA_BIT_CO3 (SLA_PORT_D3)
53 #define SLA_BIT_CO2 (SLA_PORT_D2)
54 #define SLA_BIT_CO1 (SLA_PORT_D1)
55 #define SLA_BIT_CO0 (SLA_PORT_D0)
56 
57 /*
58  * Now we define symbolic names for the bits defined above, depending
59  * on the function
60  */
61 
62 #define SLA_BIT_ID1 ( SLA_BIT_CO7 ) /* Two bits worth of chip ident */
63 #define SLA_BIT_ID0 ( SLA_BIT_CO6 )
64 #define SLA_BIT_RS ( SLA_BIT_CO5 ) /* 0 = data register, 1 = direction register */
65 #define SLA_BIT_RW ( SLA_BIT_CO4 ) /* 0 = Read, 1 = Write */
66 #define SLA_BIT_DF1 ( SLA_BIT_CO3 ) /* Two bits of data format */
67 #define SLA_BIT_DF0 ( SLA_BIT_CO2 )
68 #define SLA_BIT_CM1 ( SLA_BIT_CO1 ) /* Two bits of compare mode */
69 #define SLA_BIT_CM0 ( SLA_BIT_CO0 )
70 
71 #define SLA_BIT_LO(x) ( 0 ) /* Set the bit low in the register */
72 #define SLA_BIT_HI(x) ( x ) /* Set the bit high in the register */
73 
74 /*
75  * Now define the function of each of the bit states above
76  */
77 
78 /* Different IDs for up to 4 chips */
79 #define SLA_REG_IDENT0 (SLA_BIT_LO( SLA_BIT_ID1 ) | SLA_BIT_LO( SLA_BIT_ID0 ))
80 #define SLA_REG_IDENT1 (SLA_BIT_LO( SLA_BIT_ID1 ) | SLA_BIT_HI( SLA_BIT_ID0 ))
81 #define SLA_REG_IDENT2 (SLA_BIT_HI( SLA_BIT_ID1 ) | SLA_BIT_LO( SLA_BIT_ID0 ))
82 #define SLA_REG_IDENT3 (SLA_BIT_HI( SLA_BIT_ID1 ) | SLA_BIT_HI( SLA_BIT_ID0 ))
83 
84 /* Register selection Data/Direction Register */
85 #define SLA_REG_DATA SLA_BIT_LO( SLA_BIT_RS ) /* Select data register */
86 #define SLA_REG_DIR SLA_BIT_HI( SLA_BIT_RS ) /* Select direction register */
87 
88 #define SLA_REG_READ SLA_BIT_LO( SLA_BIT_RW ) /* Read request */
89 #define SLA_REG_WRITE SLA_BIT_HI( SLA_BIT_RW ) /* Write request */
90 
91 /* Data format defines */
92 #define SLA_REG_DF_ALL (SLA_BIT_LO( SLA_BIT_DF1 ) | SLA_BIT_LO( SLA_BIT_DF0 )) /* update all bits */
93 #define SLA_REG_DF_CLR (SLA_BIT_HI( SLA_BIT_DF1 ) | SLA_BIT_LO( SLA_BIT_DF0 )) /* Clear bits specified */
94 #define SLA_REG_DF_SET (SLA_BIT_HI( SLA_BIT_DF1 ) | SLA_BIT_HI( SLA_BIT_DF0 )) /* Set bits specified */
95 
96 /* Compare mode defines */
97 #define SLA_REG_CM_1NM (SLA_BIT_LO( SLA_BIT_CM1 ) | SLA_BIT_LO( SLA_BIT_CM0 )) /* At least one non-match */
98 #define SLA_REG_CM_AM (SLA_BIT_LO( SLA_BIT_CM1 ) | SLA_BIT_HI( SLA_BIT_CM0 )) /* All match */
99 #define SLA_REG_CM_ANM (SLA_BIT_HI( SLA_BIT_CM1 ) | SLA_BIT_LO( SLA_BIT_CM0 )) /* All are non match */
100 #define SLA_REG_CM_1M (SLA_BIT_HI( SLA_BIT_CM1 ) | SLA_BIT_HI( SLA_BIT_CM0 )) /* At least one match */
101 
102 
103 /* Macro to build up a command to the latch */
104 #define SLA_CMD( id, rs, rw, df, cm ) ( (id) | (rs) | (rw) | (df) | (cm) )
105 
106 /* The different commands available
107  *
108  * Note id is the chip id (SLA_REG_IDENTx),
109  * cm is a compare mode
110  *
111  * see chiip data sheet for details
112  */
113 #define SLA_CMD_DATA_READ( id, cm ) SLA_CMD( id, SLA_REG_READ, SLA_REG_DATA, SLA_REG_DF_ALL, cm )
114 #define SLA_CMD_DATA_WRITE( id, cm ) SLA_CMD( id, SLA_REG_WRITE, SLA_REG_DATA, SLA_REG_DF_ALL, cm )
115 #define SLA_CMD_DIR_READ( id, cm ) SLA_CMD( id, SLA_REG_READ, SLA_REG_DIR, SLA_REG_DF_ALL, cm )
116 #define SLA_CMD_DIR_WRITE( id, cm ) SLA_CMD( id, SLA_REG_WRITE, SLA_REG_DIR, SLA_REG_DF_ALL, cm )
117 
118 /*
119  * Definitions for the bits of the direction register
120  */
121 
122 #define SLA_DIR_INPUT(x) (0) /* Bit is a 0, ie pin is input */
123 #define SLA_DIR_OUTPUT(x) (x) /* Bit is a 1, ie pin is output */
124 
125 #define SLA_DIR_D0_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D0))
126 #define SLA_DIR_D1_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D1))
127 #define SLA_DIR_D2_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D2))
128 #define SLA_DIR_D3_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D3))
129 #define SLA_DIR_D4_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D4))
130 #define SLA_DIR_D5_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D5))
131 #define SLA_DIR_D6_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D6))
132 #define SLA_DIR_D7_OUTPUT (SLA_DIR_OUTPUT(SLA_PORT_D7))
133 
134 #define SLA_DIR_D0_INPUT (SLA_DIR_INPUT(SLA_PORT_D0))
135 #define SLA_DIR_D1_INPUT (SLA_DIR_INPUT(SLA_PORT_D1))
136 #define SLA_DIR_D2_INPUT (SLA_DIR_INPUT(SLA_PORT_D2))
137 #define SLA_DIR_D3_INPUT (SLA_DIR_INPUT(SLA_PORT_D3))
138 #define SLA_DIR_D4_INPUT (SLA_DIR_INPUT(SLA_PORT_D4))
139 #define SLA_DIR_D5_INPUT (SLA_DIR_INPUT(SLA_PORT_D5))
140 #define SLA_DIR_D6_INPUT (SLA_DIR_INPUT(SLA_PORT_D6))
141 #define SLA_DIR_D7_INPUT (SLA_DIR_INPUT(SLA_PORT_D7))
142 
143 
144 /*
145  * End of 2500 SPI latch definitions
146  */
147 
148 
149 
150 // base class for SPI latch messages - maps module to device
151 // and sets SPI/SCI mode to SCI
152 class SlaSpiScheduledMessage:public SpiScheduledMessage
153 {
154  public:
155  SlaSpiScheduledMessage(unsigned char module, unsigned char length);
156  virtual ~SlaSpiScheduledMessage();
157  private:
158  static unsigned short moduleToDevice(unsigned char module);
159 };
160 
161 // used to write to the SPI latch output pins
163 {
164  public:
165  SlaWriteSpiScheduledMessage(unsigned char module, SlaChipIdEnum chipSelect, unsigned char data);
166  virtual ~SlaWriteSpiScheduledMessage();
167 
168  void setData(unsigned char data);
169 };
170 
171 // sets the SPI latch data direction register (DDR)
173 {
174  public:
175  SlaDDRSpiScheduledMessage(unsigned char module,
176  SlaChipIdEnum chipSelect,
177  unsigned char dataDirection);
178  virtual ~SlaDDRSpiScheduledMessage();
179 };
180 
181 #endif /*__SLATCH_SSM_H */
182 
Definition: sla_ssm.h:162
Definition: sla_ssm.h:172
Definition: sla_ssm.h:152