18 #define DFC_STATUS_MASK (0xf0)
19 #define DFC_STATUS_OK (0x80)
28 IO_DFC_PM_VWireConf_OutDSM1,
29 IO_DFC_PM_VWireConf_OutIOC1,
30 IO_DFC_PM_VWireConf_OutDSM2,
31 IO_DFC_PM_VWireConf_OutIOC2,
32 IO_DFC_PM_VWireConf_HiZ,
33 IO_DFC_PM_VWireConf_Ch2Clk,
34 IO_DFC_PM_VWireConf_Logic0,
35 IO_DFC_PM_VWireConf_Logic1,
36 IO_DFC_PM_VWireConf_AuxFilt,
44 enum DfcDataReadyState
46 IO_DFC_PM_DataReady_Filt1Done,
47 IO_DFC_PM_DataReady_Filt2Done,
48 IO_DFC_PM_DataReady_BothDone,
49 IO_DFC_PM_DataReady_EitherDone,
50 IO_DFC_PM_DataReady_HiZ,
51 IO_DFC_PM_DataReady_Ch1Clk,
52 IO_DFC_PM_DataReady_Logic0,
53 IO_DFC_PM_DataReady_Logic1,
54 IO_DFC_PM_DataReady_AuxFilt,
60 enum DfcFilterClockDivisorEnum
62 IO_DFC_PF_ChxConf_FS_D8 = 0,
63 IO_DFC_PF_ChxConf_FS_D16 = 1,
64 IO_DFC_PF_ChxConf_FS_D32 = 2,
65 IO_DFC_PF_ChxConf_FS_D64 = 3,
66 IO_DFC_PF_ChxConf_FS_D128 = 4,
67 IO_DFC_PF_ChxConf_FS_D256 = 5,
68 IO_DFC_PF_ChxConf_FS_D8a = 6,
69 IO_DFC_PF_ChxConf_FS_D8b = 7,
79 IO_DFC_PA_ABDInt_LOGOUT = 0,
80 IO_DFC_PA_ABDInt_LOGIN = 2,
81 IO_DFC_PA_ABDInt_MLOGIN_EC = 4,
82 IO_DFC_PA_ABDInt_MLOGIN_SC = 5,
83 IO_DFC_PA_ABDInt_DSMIOC_EC = 6,
84 IO_DFC_PA_ABDInt_DSMIOC_SC = 7,
85 IO_DFC_PA_ABDInt_IOC_EC = 8,
86 IO_DFC_PA_ABDInt_IOC_SC = 9,
87 IO_DFC_PA_ABDInt_IOCData_EC = 10,
88 IO_DFC_PA_ABDInt_IOCData_SC = 11,
89 IO_DFC_PA_ABDInt_DSMData_EC = 12,
90 IO_DFC_PA_ABDInt_DSMData_SC = 13,
91 IO_DFC_PA_ABDInt_DSM_EC = 14,
92 IO_DFC_PA_ABDInt_DSM_SC = 15
95 #define IO_DFC_FVS_Saturation (0x10)
96 #define IO_DFC_FVS_DataLost (0x20)
97 #define IO_DFC_FVS_Valid (0x40)
98 #define IO_DFC_FVS_Heartbeat (0x80)
104 #define DSM_FILTER_MAX_COUNTS 0xf7641
105 #define DSM_FILTER_MIN_COUNTS 0x00000
116 DSM_CLOCK_DIV128 = 4,
154 DSM_MISC_VWIRE0 = 0x01,
155 DSM_MISC_VWIRE1 = 0x02,
156 DSM_MISC_VWIRE_TS = 0x03,
169 IOC_CLOCK_DIV128 = 4,
170 IOC_CLOCK_DIV256 = 5,
178 DsmClockEnum m_clock;
193 static unsigned short moduleToDevice(
unsigned char module);
212 void setPortABDMode(
unsigned char z_port, DfcABDModeEnum z_mode);
213 void setPortFilterTimeDivisor(
unsigned char z_port, DfcFilterClockDivisorEnum z_divisor);
214 void setVWireConfig(DfcVwireState z_state);
215 void setDataReadyConfig(DfcDataReadyState z_state);
239 long getRawFilterCount();
248 unsigned char getFilterStatus() {
return getRxPtr()[3]&0xF0; };
259 void setData(
unsigned char *datap);
270 unsigned char z_module,
271 unsigned char z_port,
274 DsmClockEnum z_clock,
280 unsigned char z_port,
283 DsmClockEnum z_clock,
287 unsigned char z_port,
294 enum DfcVWireDataReadyMessageEnum
296 DFC_VWIRE_DATA_READY_MESSAGE_VWIRE_COMMAND,
297 DFC_VWIRE_DATA_READY_MESSAGE_VWIRE_DATA,
298 DFC_VWIRE_DATA_READY_MESSAGE_CONTINUE1,
299 DFC_VWIRE_DATA_READY_MESSAGE_DATA_READY_COMMAND,
300 DFC_VWIRE_DATA_READY_MESSAGE_DATA_READY_DATA,
301 DFC_VWIRE_DATA_READY_MESSAGE_CONTINUE2,
302 DFC_VWIRE_DATA_READY_MESSAGE_LENGTH,
312 void setVwireState(DfcVwireState state){getTxPtr()[DFC_VWIRE_DATA_READY_MESSAGE_VWIRE_DATA] = state;};
313 void setDataReadyState(DfcDataReadyState state){getTxPtr()[DFC_VWIRE_DATA_READY_MESSAGE_DATA_READY_DATA] = state;};
326 unsigned char z_module,
327 unsigned char filter,
328 unsigned char filterIP);
332 void setDfcFilterConfig(
unsigned char filter,
unsigned char filterIP);
346 void setState(DfcVwireState state){getTxPtr()[1] = state;};
358 void setState(DfcDataReadyState state){getTxPtr()[1] = state;};
367 unsigned char z_module,
368 unsigned char z_port);
373 unsigned short z_count);
383 unsigned char z_module,
384 unsigned char z_port);
389 unsigned short z_count);
403 unsigned char z_module,
404 unsigned char z_port) ;
411 void setClock(IocClockEnum z_clock);
Definition: dfc_ssm.h:340
Definition: dfc_ssm.h:399
Definition: dfc_ssm.h:198
Definition: dfc_ssm.h:363
Definition: dfc_ssm.h:186
Definition: dfc_ssm.h:322
Definition: dfc_ssm.h:233
Definition: dfc_ssm.h:266
Definition: dfc_ssm.h:206
Definition: dfc_ssm.h:220
Definition: dfc_ssm.h:379
Definition: dfc_ssm.h:306
Definition: dfc_ssm.h:352
Definition: dfc_ssm.h:254
Definition: dfc_ssm.h:174