versadac  1
versadac - Scalable Recorder Firmware
dfc_ssm.h
1 /*******************************************************************************
2 FILE : dfc_ssm.h
3 VERSION : $Id$
4 AUTHOR : David Cozens
5 SYSTEM : Diab C for PowerPC under vxWorks
6 DESCRIPTION : This file contains all of the classes in a heirachy that encapsulate
7  the messages used to communicate with a dfc.
8 *******************************************************************************/
9 #ifndef __DFC_SSM_H
10 #define __DFC_SSM_H
11 #include "spismsg.h"
12 
13 /*
14  * If a continuation byte is issued on its own, when the dfc has no
15  * communication in progress, it reports the current status, the following
16  * defines show the layout of the status bits
17  */
18 #define DFC_STATUS_MASK (0xf0)
19 #define DFC_STATUS_OK (0x80)
20 
21 /*
22  *--------------------------------------------------------------------------
23  * Valuse to be used with IO_DFC_PM_VWireConf register
24  *--------------------------------------------------------------------------
25  */
26 enum DfcVwireState
27 {
28  IO_DFC_PM_VWireConf_OutDSM1, /* Source DSM on ABD Port 1*/
29  IO_DFC_PM_VWireConf_OutIOC1, /* Source IOC on ABD Port 1*/
30  IO_DFC_PM_VWireConf_OutDSM2, /* Source DSM on ABD Port 2*/
31  IO_DFC_PM_VWireConf_OutIOC2, /* Source IOC on ABD Port 2*/
32  IO_DFC_PM_VWireConf_HiZ, /* Tristate */
33  IO_DFC_PM_VWireConf_Ch2Clk, /* Channel 2 Filter Clock */
34  IO_DFC_PM_VWireConf_Logic0, /* Logic level 0 */
35  IO_DFC_PM_VWireConf_Logic1, /* Logic level 1 */
36  IO_DFC_PM_VWireConf_AuxFilt, /* Auxilary filter input */
37 };
38 
39 /*
40  *--------------------------------------------------------------------------
41  * Values to be used with IO_DFC_PM_DataReady register
42  *--------------------------------------------------------------------------
43  */
44 enum DfcDataReadyState
45 {
46  IO_DFC_PM_DataReady_Filt1Done, /* Filter 1 finished */
47  IO_DFC_PM_DataReady_Filt2Done, /* Filter 2 finished */
48  IO_DFC_PM_DataReady_BothDone, /* Both filters finished */
49  IO_DFC_PM_DataReady_EitherDone,/* Either filter finished */
50  IO_DFC_PM_DataReady_HiZ, /* Tristate */
51  IO_DFC_PM_DataReady_Ch1Clk, /* Channel 1 Filter Clock */
52  IO_DFC_PM_DataReady_Logic0, /* Logic level 0 */
53  IO_DFC_PM_DataReady_Logic1, /* Logic level 1 */
54  IO_DFC_PM_DataReady_AuxFilt, /* Auxilary filter input */
55 };
56 
57 /*
58  * Selections available for filter clock divider rate of the filter
59  */
60 enum DfcFilterClockDivisorEnum
61 {
62  IO_DFC_PF_ChxConf_FS_D8 = 0, /* divide by 8 */
63  IO_DFC_PF_ChxConf_FS_D16 = 1, /* divide by 16 */
64  IO_DFC_PF_ChxConf_FS_D32 = 2, /* divide by 32 */
65  IO_DFC_PF_ChxConf_FS_D64 = 3, /* divide by 64 */
66  IO_DFC_PF_ChxConf_FS_D128 = 4, /* divide by 128 */
67  IO_DFC_PF_ChxConf_FS_D256 = 5, /* divide by 256 */
68  IO_DFC_PF_ChxConf_FS_D8a = 6, /* divide by 8 */
69  IO_DFC_PF_ChxConf_FS_D8b = 7, /* divide by 8 */
70 };
71 
72 /*
73  *--------------------------------------------------------------------------
74  * Interface modes used with the IO_DFC_PA_ABDInt register
75  *--------------------------------------------------------------------------
76  */
77 enum DfcABDModeEnum
78 {
79  IO_DFC_PA_ABDInt_LOGOUT = 0, /* Direct logic output */
80  IO_DFC_PA_ABDInt_LOGIN = 2, /* Direct logic input */
81  IO_DFC_PA_ABDInt_MLOGIN_EC = 4, /* Multiple logic inp (EC) */
82  IO_DFC_PA_ABDInt_MLOGIN_SC = 5, /* Multiple logic inp (SC) */
83  IO_DFC_PA_ABDInt_DSMIOC_EC = 6, /* Combined DSM & IOC (EC) */
84  IO_DFC_PA_ABDInt_DSMIOC_SC = 7, /* Combined DSM & IOC (SC) */
85  IO_DFC_PA_ABDInt_IOC_EC = 8, /* IOC Only EC No data rtn */
86  IO_DFC_PA_ABDInt_IOC_SC = 9, /* IOC Only SC No data rtn */
87  IO_DFC_PA_ABDInt_IOCData_EC = 10, /* IOC Only EC data return */
88  IO_DFC_PA_ABDInt_IOCData_SC = 11, /* IOC Only SC data return */
89  IO_DFC_PA_ABDInt_DSMData_EC = 12, /* DSM Only EC data return */
90  IO_DFC_PA_ABDInt_DSMData_SC = 13, /* DSM Only SC data return */
91  IO_DFC_PA_ABDInt_DSM_EC = 14, /* DSM Only EC no data rtn */
92  IO_DFC_PA_ABDInt_DSM_SC = 15 /* DSM Only SC no data rtn */
93 };
94 
95 #define IO_DFC_FVS_Saturation (0x10)
96 #define IO_DFC_FVS_DataLost (0x20)
97 #define IO_DFC_FVS_Valid (0x40)
98 #define IO_DFC_FVS_Heartbeat (0x80)
99 
100 /*
101  * Max and minimum counts allowed from the cosine filter. If either of
102  * these numbers are locked up then we are seriously dead
103  */
104 #define DSM_FILTER_MAX_COUNTS 0xf7641
105 #define DSM_FILTER_MIN_COUNTS 0x00000
106 
107 /*
108  * Enum for the diferent clocks available in the DSM
109  */
110 enum DsmClockEnum
111 {
112  DSM_CLOCK_DIV8 = 0, /* Divide by 8 clock */
113  DSM_CLOCK_DIV16 = 1, /* Divide by 16 clock */
114  DSM_CLOCK_DIV32 = 2, /* Divide by 32 clock */
115  DSM_CLOCK_DIV64 = 3, /* Divide by 64 clock */
116  DSM_CLOCK_DIV128 = 4, /* Divide by 128 clock */
117  DSM_CLOCK_DIV256 = 5 /* Divide by 256 clock */
118 };
119 
120 
121 /*
122  * Enum for the gain setting required
123  */
124 enum DsmGainEnum
125 {
126  DSM_GAIN_1_EX = 0, /* Gain of 1 with external atten */
127  DSM_GAIN_2_EX = 1, /* Gain of 2 with external atten */
128  DSM_GAIN_1 = 2, /* Gain of 1 */
129  DSM_GAIN_2 = 3, /* Gain of 2 */
130  DSM_GAIN_4 = 4, /* Gain of 4 */
131  DSM_GAIN_10 = 5, /* Gain of 10 */
132  DSM_GAIN_20 = 6, /* Gain of 20 */
133  DSM_GAIN_40 = 7 /* Gain of 40 */
134 };
135 
136 /*
137  * Enum for the multiplexor values
138  */
139 enum DsmMuxEnum
140 {
141  DSM_MUX_ANIN1 = 0, /* Select analog channel 1 */
142  DSM_MUX_ANIN2 = 1, /* Select analog channel 2 */
143  DSM_MUX_ANIN3 = 2, /* Select analog channel 3 */
144  DSM_MUX_ANIN4 = 3, /* Select analog channel 4 */
145  DSM_MUX_NONE = 4, /* Select none */
146  NUMBER_OF_DSM_MUX
147 };
148 
149 /*
150  * The miscellaneous register is 3 bits each defined as below
151  */
152 enum DsmMiscEnum
153 {
154  DSM_MISC_VWIRE0 = 0x01, /* Misc control bit 0 (Set Vwire to low) */
155  DSM_MISC_VWIRE1 = 0x02, /* Misc control bit 1 (Set Vwire to high) */
156  DSM_MISC_VWIRE_TS = 0x03, /* Vwire is tristate */
157  DSM_MISC_SB = 0x04, /* Enable sensor break */
158 };
159 
160 /*
161  * enum for the diferent clocks available in the IOC
162  */
163 enum IocClockEnum
164 {
165  IOC_CLOCK_DIV8 = 0, /* Divide by 8 clock */
166  IOC_CLOCK_DIV16 = 1, /* Divide by 16 clock */
167  IOC_CLOCK_DIV32 = 2, /* Divide by 32 clock */
168  IOC_CLOCK_DIV64 = 3, /* Divide by 64 clock */
169  IOC_CLOCK_DIV128 = 4, /* Divide by 128 clock */
170  IOC_CLOCK_DIV256 = 5, /* Divide by 256 clock */
171 };
172 
173 
174 typedef struct
175 {
176  DsmMuxEnum m_mux;
177  DsmMiscEnum m_misc;
178  DsmClockEnum m_clock;
179  DsmGainEnum m_gain;
181 
182 
183 
184 // this is the base class for all dfc transactions. It only provides
185 // module to device mapping.
186 class DfcSpiScheduledMessage:public SpiScheduledMessage
187 {
188  public:
189  DfcSpiScheduledMessage(unsigned char module, unsigned char length);
190  virtual ~DfcSpiScheduledMessage();
191 
192  private:
193  static unsigned short moduleToDevice(unsigned char module);
194 };
195 
196 // this simple class sends a single dfcContinue byte to the DFC
197 // it is used on the T2500 AI2/AI4 to bring the DFC out of reset
199 {
200  public:
201  DfcDelaySpiScheduledMessage(unsigned char module);
202  virtual ~DfcDelaySpiScheduledMessage();
203 };
204 
205 // This class completely configures a dfc
207 {
208  public:
209  DfcTotalConfigSpiScheduledMessage(unsigned char module);
211 
212  void setPortABDMode(unsigned char z_port, DfcABDModeEnum z_mode);
213  void setPortFilterTimeDivisor(unsigned char z_port, DfcFilterClockDivisorEnum z_divisor);
214  void setVWireConfig(DfcVwireState z_state);
215  void setDataReadyConfig(DfcDataReadyState z_state);
216  bool wasCommandOk();
217 };
218 
219 // This class reads back the config of a dfc and compares it with a dfc total config message
221 {
222  public:
225 
226  bool wasCommandOk();
227 
228  private:
229  DfcTotalConfigSpiScheduledMessage *m_writtenConfig;
230 };
231 
232 // This class encapsulates reading raw filter counts
234 {
235  public:
236  DfcReadFilterCountSpiScheduledMessage(unsigned char module, unsigned char port);
238 
239  long getRawFilterCount();
240 
241  /*------------------------------------------------------------------------------
242  FUNCTION : getFilterStatus
243  DESCRIPTION : Gets the most recent filter status
244  ARGUMENTS :
245  RETURN : Filter status
246  NOTES :
247  ------------------------------------------------------------------------------*/
248  unsigned char getFilterStatus() { return getRxPtr()[3]&0xF0; };
249 
250  private:
251 };
252 
253 // This class encapsulates writing command and data to the DFC
255 {
256  public:
257  DfcWriteCommandDataSpiScheduledMessage(unsigned char module, unsigned char length);
259  void setData(unsigned char *datap);
260  bool wasCommandOk();
261 
262  private:
263 };
264 
265 // This class encapsulates a DSM total configuration message
267 {
268  public:
270  unsigned char z_module,
271  unsigned char z_port,
272  DsmMuxEnum z_mux,
273  DsmMiscEnum z_misc,
274  DsmClockEnum z_clock,
275  DsmGainEnum z_gain);
276 
278 
279  void setTotalConfig(
280  unsigned char z_port,
281  DsmMuxEnum z_mux,
282  DsmMiscEnum z_misc,
283  DsmClockEnum z_clock,
284  DsmGainEnum z_gain);
285 
286  void setTotalConfig(
287  unsigned char z_port,
288  DsmTotalConfigDataType *z_data);
289 
290  private:
291 };
292 
293 // this enumerates the various bytes sent in a dfc total config message
294 enum DfcVWireDataReadyMessageEnum
295 {
296  DFC_VWIRE_DATA_READY_MESSAGE_VWIRE_COMMAND,
297  DFC_VWIRE_DATA_READY_MESSAGE_VWIRE_DATA,
298  DFC_VWIRE_DATA_READY_MESSAGE_CONTINUE1,
299  DFC_VWIRE_DATA_READY_MESSAGE_DATA_READY_COMMAND,
300  DFC_VWIRE_DATA_READY_MESSAGE_DATA_READY_DATA,
301  DFC_VWIRE_DATA_READY_MESSAGE_CONTINUE2,
302  DFC_VWIRE_DATA_READY_MESSAGE_LENGTH,
303 };
304 
305 // This class encapsulates driving the DFC VWIRE and Data Ready outputs in a single message
307 {
308  public:
309  DfcVWireDataReadySpiScheduledMessage(unsigned char module, DfcVwireState vwireState, DfcDataReadyState dwState);
311 
312  void setVwireState(DfcVwireState state){getTxPtr()[DFC_VWIRE_DATA_READY_MESSAGE_VWIRE_DATA] = state;};
313  void setDataReadyState(DfcDataReadyState state){getTxPtr()[DFC_VWIRE_DATA_READY_MESSAGE_DATA_READY_DATA] = state;};
314 
315  private:
316 };
317 
318 // This class encapsulates a DFC filter IP configuration message
319 // This implementation defaults to values required by the AI3 module which
320 // multiplexes the input to filter 1 between channel 1 DSM (connected to DFC pin
321 // D1A) and channel 2 DSM (connected to DFC pin D1B/VWO) on successive samples
323 {
324  public:
326  unsigned char z_module,
327  unsigned char filter,
328  unsigned char filterIP);
329 
331 
332  void setDfcFilterConfig(unsigned char filter, unsigned char filterIP);
333 
334  private:
335 };
336 
337 
338 
339 // This class encapsulates driving the DFC VWIRE output
341 {
342  public:
343  DfcVWireSpiScheduledMessage(unsigned char module, DfcVwireState state);
344  virtual ~DfcVWireSpiScheduledMessage();
345 
346  void setState(DfcVwireState state){getTxPtr()[1] = state;};
347 
348  private:
349 };
350 
351 // This class encapsulates driving the DFC DataReady output
353 {
354  public:
355  DfcDataReadySpiScheduledMessage(unsigned char module, DfcDataReadyState state);
357 
358  void setState(DfcDataReadyState state){getTxPtr()[1] = state;};
359  private:
360 };
361 
362 // This class encapsulates driving the output on an IOC
364 {
365  public:
367  unsigned char z_module,
368  unsigned char z_port);
369 
371 
372  void setDemandCount(
373  unsigned short z_count);
374 
375  private:
376 };
377 
378 // This class encapsulates limiting the output on an IOC
380 {
381  public:
383  unsigned char z_module,
384  unsigned char z_port);
385 
387 
388  void setDemandCount(
389  unsigned short z_count);
390 
391  private:
392 };
393 
394 
395 // This class encapsulates the IOC total config message
396 // This initial implementation defaults to the settings on
397 // a 2500 AO2 module. It is fully expected that other accessor
398 // functions will be required to make it usable on other products.
400 {
401  public:
403  unsigned char z_module,
404  unsigned char z_port) ;
405 
407 
408  void setDout(
409  bool z_dout);
410 
411  void setClock(IocClockEnum z_clock);
412 
413  private:
414 };
415 
416 
417 #endif /*__DFC_SSM_H */
418 
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